This invention relates to data communication, and more particularly to circuitry for receiving data signals that have been communicated from a data signal source.
Data is frequently transmitted serially. The serial data typically takes the form of a logic HIGH or a logic LOW as it is being transmitted. As such, the data can be transmitted as a series of zeros and ones to represent bytes of information that are being transmitted one after another. Typically, transmission of serial data can occur at relatively high speed (e.g., on the order of gigahertz). High-speed serial interface (HSSI) applications is one example that uses high speed serial transmission.
It is known that prolonged runs of a logic HIGH or logic LOW signal can cause problems in data communication. For example, DC biasing is a common problem resulting from long runs of a logic LOW or HIGH signal. DC biasing can cause the average voltage of the serial data to exhibit the voltage of the logic signal that is being repeated. This can lead to intersignal interference because a transition in the received data (e.g., a transition from a repeating logic state to the non-repeating logic state and back to the repeating logic state) may be missed. Thus, it is desirable to minimize occurrences of long runs of a particular logic state.
Run-length detection circuitry has been developed to detect occurrences of runs of a particular length. In general, run-length detection circuitry compares the number of consecutive ones or zeros received as serial data to a programmable run-length violation parameter. This parameter can be set, for example, by a multi-bit control input programmed by a user. During operation, a run-length violation signal is generated when the run length of received data exceeds the run-length violation parameter. This run-length violation signal may trigger utilization circuitry (e.g., a programmable logic device) to, for example, ignore incoming data, initiate a restart in data reception, or perform some other error control function.
Utilization circuitry is typically circuitry that processes the received data by, for example, performing logic operations. Because utilization circuitry is processing the received data, it is preferable to check the incoming data for run-length violations before it is received by the utilization circuitry. Therefore, run-length detection circuitry generally checks the data for run-length violations before it is received by the utilization circuitry. In some applications, run-length detection circuitry is part of dedicated circuitry (e.g., receiving circuitry) that conditions the serial data signal before it reaches the utilization circuitry. The dedicated circuitry can condition the data by, for example, deseriallizing the serial data and dividing down the clocking frequency of the serially transmitted data to a deserialized (slower) clocking frequency. This deseriallization is one source that creates the presence of a different clock domain (i.e., a parallel and a serial clock domain). In fact, several different clock domains may be present in the dedicated circuitry and utilization circuitry.
Previous run-length detection circuitry has operated in the serial clock domain. That is, it used the clocking frequency of serial data to detect runs in data being transmitted to the dedicated circuitry (e.g., receiving circuitry) and/or utilization circuitry. Operating run-length detection circuitry in the serial domain places several stringent design and operational requirements on the detection circuitry. For example, because there is other circuitry operates at a slower clocking frequency (e.g., a deserialized or parallel clocking frequency), the detection circuitry has to generate a run-length violation signal that can be detected by the circuitry operating in the slower clock domain. That is, the run-length violation signal may be asserted according to a predetermined number of serial domain clock cycles, but the signal may not be asserted long enough for the utilization circuitry to detect it. Thus the presence of multiple clock domains puts several design limitations on existing run-length detection circuitry, especially since serial clocking frequencies continue to increase.
Another problem with run-length detectors operating in the serial domain is that detection of runs becomes more difficult and unreliable as the length of the runs increase.
Therefore, it is an object of this invention to operate run-length violation circuitry in a slower, non-serial, clock domain.
It is also an object of this invention to asynchronously assert a run-length violation signal to ensure that utilization circuitry captures the asserted violation signal, despite the presence of multiple clock domains.